Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include one or more semiconductor dies mounted on a substrate and encased in a plastic protective covering or covered by a heat-conducting lid. The die can include functional features, such as memory cells, processor circuits, and/or imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
Semiconductor manufacturers continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the functional capacity of a semiconductor package without substantially increasing the surface area covered thereby (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies. In anticipation of electrically coupling such dies, the bond pads of dies may be provided with an electrical connection structure, such as a pillar extending upwardly from a bond pad of the die, before the dies are assembled into a package.
To avoid packaging a defective or “bad” die with a number of working or “good” dies (and thereby potentially rendering all of the dies in a package unusable), dies may be tested before assembly to identify good and bad dies. One test used to identify known good dies is a burn-in test, in which multiple (e.g., many, or even all) of the electrical circuits of a die are exercised for an extended duration, optionally at an elevated device temperature (e.g., provided by conducting the burn-in testing in a burn-in oven or with another heating apparatus). As the complexity of the integrated circuits within semiconductor dies continues to increase, along with the number of electrical connection structures used for interconnecting multiple dies, the scale of the electrical connection structures has continued to shrink to such a degree that the act of electrically connecting the electrical connection structures to a testing device (e.g., with probe pins or the like) can irreparably damage the electrical connection structure. Accordingly, it is desirable to provide methods and structures for testing semiconductor devices in a way that prevents damage to electrical connection structures used for connecting a die in a semiconductor device package.